1. Technical Field
The present invention relates to a system and method for predictive early allocation of stores in a microprocessor. More particularly, the present invention relates to a system and method for deallocating a store data queue entry when the store data queue entry includes an interruptible instruction tag that matches a completing instruction tag.
2. Description of the Related Art
Today's processors use a store data queue as a “staging” area to store data into memory. As a processor encounters an instruction to store data, the processor identifies an available entry in the store data queue and stores the instruction's instruction tag (ITAG), along with the data, into the available store data queue entry. The store data queue entry holds the data until the corresponding instruction begins completing, at which time the store data queue stores the data into memory and deallocates the store data queue entry. This deallocation makes the store data queue entry available for other instructions.
A challenge found with existing art is that a processor's pipeline may stall when it attempts to process a store instruction at a time at which the store data queue does not have an available store data queue entry. In this case, the pipeline waits until a store data queue entry is deallocated and, at that time, stores the instruction's tag, along with the data, into the deallocated store data queue entry.
One approach to minimize pipeline stalls is to increase the number of store data queue entries in a store data queue. A challenge found with this approach, however, is that increasing the number of store data queue entries increases a processor's silicon cost and power requirements.
What is needed, therefore, is a system and method to minimize processor stalls by increasing store data queue entry availability without increasing a processor's silicon and power requirements.